USB-based fast data transmission system design

              Abstract: This paper introduces a fast USB-based reading system design method. The system uses CY7C68013 achieved, the article gives the system hardware design, FPGA internal integration software implementation of FIFO method and GPIF handshake signals with the FLASH design. Through this USB data transfer module, achieved a FLASH memory and high-speed transmission of data between computers. Application results show that the data communication system is reliable and effective, with a certain degree of generality, can be used for testing other similar storage systems.
                Keywords: USB; GPIF; data transmission; FPGA
                At present the computer cable data transmission mainly serial, parallel, and USB of three. The maximum transmission speed serial port is only 115200bit / s. There are two parallel transmission mode, the EPP mode of the fastest transmission speed of about 200 of its K. The USB in the way the form of data packets transmitted, the mode of sub-low-speed, full-speed and high-speed, low speed transmission rate of 1.5M / S, full-speed around 12M / S, high-speed up to 480M / S. The face of today increasingly large-capacity storage systems, the use of USB technology, will greatly enhance the reading speed of the system. With the development of embedded systems, will the hardware USB transceiver, SIE serial interface engine, USB hardware such as integrated in a microcontroller chip, to simplify USB protocol for us to use the USB-reading module possible.
This USB transmission system uses microprocessor CY68013 achieved. This article gives the data transmission system hardware design, highlighting the FPGA control module within the integrated implementation of FIFO method and the GPIF handshake signals to communicate with the FLASH design.
                A system hardware design
                CY68013 is a Cypress introduced the EZ-USB FX2 family of products with integrated USB 2.0 transceiver, Smart Serial Engine (SIE), enhanced 8051 controller, general-purpose programmable interface (GPIF), 8.5KB of RAM and FIFO memory, the maximum bus bandwidth to meet the USB2.0. FX2 most commonly used data transmission is GPIF. GPIF is a fast data transfer method, timing easy. It can be easily read data from RAM. However, FLASH memory reading operation is based on units of pages, reading pages and pages, when a short time interval between the data output is not continuous. To resolve this issue and realize the FX2GPIF way to read FLASH data, need to use the FIFO as a data transition, the data in the FLASH first FIFO read in, USB controller, and then read the data from the FIFO.
                2FPGA internal integration software design FIFO
                2.1 The internal structure of an integrated FIFO
                FIFO is essentially a special kind of dual-port RAM, as most have dual-port RAM within the FPGA resources. So here, the appropriate choice of FPGA chips to write the internal FPGA integrated FIFO. FIFO FIFO structure is characterized by the outside does not address control it is a special cache. As long as to provide a FIFO read, write enable signal will be able to make it work, only difference is that the external FIFO address is not displayed, but given the performance of the internal state of full, half-full and empty signal, the user based on these signals to the FIFO to operate.
                FIFO design of the most important thing is how these signals are given. This design produces FIFO full, half-full and empty state of signs and signals using the following methods: Using read address and write address subtraction results to determine the full FIFO empty state; also could then be half-full FIFO, the status signal. This method can easily control the FIFO full, half full, empty depth.
                2.2FIFO signs and signals generation
                FIFO full, empty, half full flag signal generation process is the same, but the difference compared to judge not the same. FIFO full when the margin of 1023, and air is 1. In order to avoid timing errors, you can also set a certain depth of the full space. For example, when the address that the difference is greater than 1000 when the FIFO is full and no longer write data to the FIFO, so that to avoid errors.
                3GPIF with FLASH handshake signal design is full, empty the signal is mainly used in the readings used when reading GPIF with FLASH handshake signals to ensure stable and reliable readings. When reading the data first deposit into the FIFO, and then USB and then read the data from the FIFO. For the FIFO, the read and write speed is different, may be read faster than the writing may also be faster to write than read. Therefore, we need to design readings handshake signals, to prevent loss of data when reading. Signal handshake process is: For the reading of control modules for dissatisfaction with it as long as the FIFO write data to the FIFO. For the FX2GPIF, as long as FIFO is not empty it will read data from the FIFO. Under such circumstances, FIFO read and write on the formation of a closed loop to ensure complete and accurate readings. Reposted elsewhere in the Research Papers Download http://www.hi138.com
                After reading handshake determine two situations may arise: ① FIFO write faster than the number of reading speed, so write address have slowly catch up with the reading of addresses, and then the overall speed of the reading speed by reading the decision. ② FIFO write faster than the number of reading speed, so read slowly to catch up with the address to write addresses, when the overall reading speed on the speed of the decision by writing a few.
                4 Conclusion
                This design of microprocessor-based EZ-USB FX2 data communication system to realize the use of USB ports from the kinds of FLASH memory to read data quickly. This data communication system used in a certain type of vehicle testing storage systems. Through this transfer of data stored in the module to quickly read into the computer, according to host computer data recovery signal and original signal compared to the smaller distortion, low noise level achieved good results. This design has some versatility for most USB-based high-speed data transmission system design has a certain Application reference value.
References:
[1] Qian Feng. EZ-USB FX2 microcontroller principle, Programming and Applications [M]. Beijing: Beijing University of Aeronautics and Astronautics Press, 2006.
[2] Zhang Xin, Wang Hongliang. Universal asynchronous serial communications test system [J]. Journal of Scientific Instrument, 2006,27 (S2) :434-435.
[4] Xu Yuan, Zhang Tian-Xu. USB Bus-based high-speed video acquisition system design [J]. Micro-computer information, 2006, (10): 247. Reposted elsewhere in the Research Papers Download http://www.hi138.com