DSP HPI bus and MPC8272 bus interface FPGA implementation

Paper Keywords: DSP HPI MPC8272 FPGA VHDL source code
Abstract: Based on the TI TMS320C6421 DSP HPI interface signals the company and the interface bus timing analysis to VHDL language as a tool, using Altera's FPGA chip EP3C40F780C8, MPC8272 bus design is completed and TMS320C6421 DSP HPI communication interface between bus and in the actual use of products that have been given the entire interface design associated with the VHDL source code. For a similar DSP HPI interface design, this article has a reference and guide.

One, HPI Overview
HPI (Host-Port Interface) host interface, high performance TI DSP is configured to communicate with the host-chip peripherals. Through the HPI interface, the host can easily access all the DSP address space, enabling the DSP control.

TMS320C6421 the HPI interface is a 16bit wide parallel port. Host (host) on the CPU address space access is achieved through the EDMA controller. HPI interface to access, mainly through three dedicated registers to achieve, they are HPI control register (HPIC), HPI address register (HPIA) and the HPI data register (HPID).

Second, HPI interface signals Profile
(1) HD [15:0] (data bus)
(2) HCNTL [1:0] (control HPI access type)
As mentioned earlier of HPI need access to three registers, the HPI address register (HPIA), HPI data register (HPID) and the HPI control register (HPIC) to achieve. HCNTL [1:0] register is used to select these three dedicated pins.