Of Digital IC Design Technology

Abstract: With the design of digital circuits increase the size and complexity of its design time and cost spent also will be increased. According to recent statistics, the design of digital systems the time spent on the entire development process accounted for more than 60%. So it takes practice to reduce the cost of design digital circuit design and development of the current key, which must be a breakthrough design approach.

Keywords: digital system; IC; design

a digital IC design methodology

CI in the current design, the number of CI-based timing-driven design methodology is based on reuse design of digital CI method, based on an integrated platform for system-level design of digital CI CI design is more popular in today's digital 3 main types of design methods, which are multiplexed based on the number of CI CI design method is effective in improving the design of key technologies. It can solve today's chip design industry faces a series of challenges: to shorten the design cycle, provide better performance, faster, more cost digital IC chip.

Based timing-driven design method, described in both HDL or schematic design, timing optimization feature lies in the goal of focusing on gate-level circuit design, with a new circuit to achieve the system function; This approach for the completion of small-scale ASIC design. For large-scale system-level circuit, even if the team, always from the gate-level structure in order to achieve optimal design, it is difficult to ensure the design cycle is short, fast time to market requirements.

Reuse based on the number of CI PI design method to meet the requirements of the chip size increases, more and shorter design cycles required demands, characterized by a positive function of CI design reuse and combination of modules. This approach to design digital CI, CI number is the module that contains a variety of reuse, the development of digital CI can be divided into modules with the completion of development and systems integration. Focus on the positive multiplexing is how the system functions of the structure of division, how to define the on-chip bus interconnect module, should select those modules, each module in the definition of how to consider the positive as much as possible the use of existing resources rather than re-development of design in the functional module can be beneficial to consider how to define the future are re-used, how the system verification.

Reuse based on the number of CI PI design method, its main feature is the function of the module assembly, the technology lies in the following three aspects: First, the positive development of reusable soft-core, hard core; the second is what to do better IP reuse, functional assembly, to meet the needs of target CI; third is how to verify the completion of the number of CI assembly meets the definition of functional and timing specifications.


Second, the typical digital IC development process

number of CI development process typically includes the following major steps of 24 aspects:
(1) to determine the overall IC design specifications and make .

(2) RTL code is written and ready to etshtnehc code.

(3) contains the storage unit for design, RTL coding to insert BIST (built-in self test) circuit.

(4) functional simulation to verify design functions correctly.

(5) complete the design integrated, generate gate-level netlist.

(6) completion of DFT (Design for Testability) design.

(7) in the synthesis tool to complete the module-level static timing analysis and processing.

(8) form of authentication. Comparison table to achieve integrated network functionality is consistent with the TRL level description.

(9) Pre entire design a layout static timing analysis.

(10) to integrated time constraints when passed to the layout tool.

(11) sampling strategy for timing-driven initialization nooprlna. Include unit distribution, generated clock tree
(12) gave the clock tree synthesis tool and inserted into the initial integrated network table.

(13) formal verification. Contrast into the clock tree synthesis netlist and the initial implementation of integrated network functionality are the same table.

(14) in step (11) after the extraction potential is estimated wiring delay information.

(15) to step (14), the delay information extracted from a comprehensive anti-standard tools and static timing analysis tools.

(16) static timing analysis. Extracted using standard estimates of post-layout delay information.

(17) in the synthesis tool to implement on-site timing optimization (optional).

(18) to complete the detailed wiring.

(19) from the completion of the detailed design of wiring delay in the extraction of detailed information.

(20) to step (19) delay information extracted from a comprehensive anti-standard tools and static timing analysis tools.

(21) Post-layout static timing analysis.

(22) in the synthesis tool to implement on-site timing optimization (optional).

(23) Post a alyout functional simulation netlist (optional).

(24) after the output of the design layout physical verification data to the chip factory.

For any CI product development, the first is always demand from the markets the concept of the information or products, demand for these concepts, CI CI engineers and gradually complete the definition of specifications and overall program design. Definition of the overall program the chip division of functions and modules, the module defines functions and modules and so the timing. Been fully discussed in the overall program or demonstration of product development after CI. CI development phase includes design entry, functional simulation, synthesis, DFT (Design for Testability), formal verification, static timing analysis, layout and so on. The CI of the back-end design including layout, clock tree insertion, routing and physical verification, etc., back-end design is generally done automatically in software, such as the SIE will be able to automatically place and route software.

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